 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CY62256V 256K (32K x 8) Static RAM Features * High Speed -- 70 ns * Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive: -40C to 125C * Low voltage range: -- 2.7V - 3.6V * Low active power and standby power * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power * Available in a Pb-free and non Pb-free standard 28-pin narrow SOIC, 28-pin TSOP-1 and 28-pin Reverse TSOP-1 packages Functional Description[1] The CY62256V family is composed of two high-performance CMOS static RAM's organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and Tri-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. Logic Block Diagram INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5 32K x 8 ARRAY COLUMN DECODER POWER DOWN I/O6 I/O7 Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05057 Rev. *F * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 25, 2006 [+] Feedback CY62256V Product Portfolio Power Dissipation VCC Range (V) Product CY62256VLL Range Com'l/Ind'l Automotive Min. 2.7 Typ.[2] 3.0 Max. 3.6 Speed (ns) 70 Operating, ICC (mA) Typ.[2] 11 Max. 30 Standby, ISB2 (A) Typ.[2] 0.1 Max. 5 130 Pin Configurations Narrow SOIC Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE 7 6 5 4 3 2 1 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 TSOP I Reverse Pinout Top View (not to scale) A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TSOP I Top View (not to scale) A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 Pin Definitions Pin Number 1-10, 21, 23-26 11-13, 15-19 27 20 22 Input Input/Output Input/Control Input/Control Input/Control Type A0-A14. Address Inputs I/O0-I/O7. Data lines. Used as input or output lines depending on operation WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are Tri-stated, and act as input data pins GND. Ground for the device VCC. Power supply for the device Description 14 28 Ground Power Supply Note: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C, and tAA = 70 ns. Document #: 38-05057 Rev. *F Page 2 of 12 [+] Feedback CY62256V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V DC Input Voltage .................................-0.5V to VCC + 0.5V [3] Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Device Range Ambient Temperature (TA)[4] 0C to +70C -40C to +85C -40C to +125C VCC 2.7V to 3.6V CY62256V Commercial Industrial Automotive Electrical Characteristics Over the Operating Range CY62256V-70 Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VIN < VCC Com'l, Ind'l Automotive IOZ Output Leakage Current GND < VIN < VCC, Output Disabled Com'l, Ind'l Automotive ICC ISB1 ISB2 VCC Operating Supply Current VCC = 3.6V, IOUT = 0 mA, f = fMax = 1/tRC Automatic CE Power-down Current-- TTL Inputs Automatic CE Power-down Current-- CMOS Inputs VCC = 3.6V, CE > VIH, VIN > VIH or VIN < VIL, f = fMax All ranges All ranges IOH = -1.0 mA IOL = 2.1 mA Test Conditions VCC = 2.7V VCC = 2.7V 2.2 -0.5 -1 -10 -1 -10 11 100 0.1 0.1 0.1 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +10 +1 +10 30 300 5 10 130 Typ.[2] Max. Unit V V V V A A A A mA A A Com'l VCC = 3.6V, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Ind'l Automotive Notes: 3. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 4. TA is the "Instant-On" case temperature. Document #: 38-05057 Rev. *F Page 3 of 12 [+] Feedback CY62256V Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF Thermal Resistance Parameter JA JC Description Thermal Resistance (Junction to Ambient)[6] Thermal Resistance (Junction to Case)[5] Test Conditions Still Air, soldered on a 3 x 4.5 inch, 2-layer printed circuit board SOIC 68.45 26.94 TSOPI 87.62 23.73 RTSOPI 87.62 23.73 Unit C/W C/W AC Test Loads and Waveforms R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND < 5 ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH ALL INPUT PULSES 90% 90% 10% < 5 ns Parameter R1 R2 RTH VTH 3.3V 1100 1500 645 1.750 Units Ohms Ohms Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = 1.4V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Com'l Ind'l Auto tCDR[6] tR[6] Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC Conditions[6] Min. 1.4 0.1 0.1 0.1 3 6 50 ns ns Typ.[2] Max. Unit V A Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.4V VCC(min) tR CE Notes: 5. Tested initially and after any design or process changes that may affect these parameters. 6. No input may exceed VCC + 0.3V. Document #: 38-05057 Rev. *F Page 4 of 12 [+] Feedback CY62256V Switching Characteristics Over the Operating Range[7] CY62256V-70 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[8, 9] 10 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[8] OE HIGH to High-Z[8, 9] 10 25 0 70 5 25 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit CE LOW to Low-Z[8] CE HIGH to High-Z[8, 9] CE LOW to Power-up CE HIGH to Power-down WE HIGH to Low-Z[8] Notes: 7. Test conditions assume signal transition time of 5 ns or less timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOL/IOH and 50 pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05057 Rev. *F Page 5 of 12 [+] Feedback CY62256V Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] t RC CE tACE OE tDOE t LZOE HIGH IMPEDANCE tLZCE t PU VCC SUPPLY CURRENT 50% t PD ICC 50% ISB t HZOE tHZCE DATA VALID HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (WE Controlled)[10, 15, 16] tWC ADDRESS CE tAW tSA WE t PWE tHA OE tSD DATA I/O NOTE 17 t HZOE DATAINVALID tHD Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05057 Rev. *F Page 6 of 12 [+] Feedback CY62256V Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[10, 15, 16] tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAINVALID t HD tHA tSCE Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16] tWC ADDRESS CE tAW tSA WE tSD DATA I/O NOTE 17 t HZWE DATA INVALID tLZWE t HD t HA Document #: 38-05057 Rev. *F Page 7 of 12 [+] Feedback CY62256V Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 NORMALIZED ICC NORMALIZED I CC 1.2 1.0 0.8 0.6 0.4 0.2 2.4 2.8 1.6 1.8 2.0 3.2 3.6 TA= 25C 1.4 1.2 1.0 ISB2 A 0.8 0.6 0.4 0.2 0.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 NORMALIZED t AA AA NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE VCC = 3.0V STANDBY CURRENT vs. AMBIENT TEMPERATURE 3.0 2.5 2.0 VCC = 2.5V V cc 0.0 25 125 -0.5 -55 -55 25 V 0.5 ISB cc = 2. 5V 1.0 = 3. 3V 1.5 105 AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 VCC = 3.0V AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT 14 vs. OUTPUT VOLTAGE 12 10 8 6 VCC = 2.5 V 2.0 1.4 VCC = 2.5V 1.5 1.0 0.5 0.0 1.65 TA = 25C 1.2 1.0 0.8 0.6 OUTPUT SINK CURRENT (mA) NORMALIZED t 4 2 0 0.0 1.0 TA = 25C 2.1 2.6 3.1 3.6 -55 25 125 2.0 3.0 SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT (mA) AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE -14 -12 -10 -8 -6 -4 0 0.0 0.5 1.0 1.5 2 2.5 VCC = 2.5V TA = 25C OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Document #: 38-05057 Rev. *F Page 8 of 12 [+] Feedback CY62256V Typical DC and AC Characteristics (continued) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED ICC DELTA tAA (ns) 25.0 T = 25C A VCC = 3V 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 0.50 1 10 20 30 NORMALIZED I CC vs.CYCLE TIME 1.25 VCC = 3.0V 1.00 TA = 25C VIN = 0.5V 0.75 CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Mode Deselect/Power-down Read Write Deselect, Output Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 70 Ordering Code CY62256VLL-70SNC CY62256VLL-70SNXC CY62256VLL-70ZC CY62256VLL-70ZXC CY62256VLL-70SNXI CY62256VLL-70ZI CY62256VLL-70ZXI CY62256VLL-70ZRI CY62256VLL-70ZRXI CY62256VLL-70SNE CY62256VLL-70SNXE CY62256VLL-70ZE CY62256VLL-70ZXE CY62256VLL-70ZRE CY62256VLL-70ZRXE 51-85074 51-85071 51-85092 51-85074 51-85092 51-85071 51-85071 Package Diagram 51-85092 Package Type 28-pin (300-mil Narrow Body) SNC 28-pin (300-mil Narrow Body) SNC (Pb-Free) 28-pin TSOP I 28-pin TSOP I (Pb-Free) 28-pin (300-mil Narrow Body) SNC (Pb-Free) 28-pin TSOP I 28-pin TSOP I (Pb-Free) 28-pin Reverse TSOP I 28-pin Reverse TSOP I (Pb-Free) 28-pin (300-mil Narrow Body) SNC 28-pin (300-mil Narrow Body) SNC (Pb-Free) 28-pin TSOP I 28-pin TSOP I (Pb-Free) 28-pin Reverse TSOP I 28-pin Reverse TSOP I (Pb-Free) Automotive Industrial Operating Range Commercial Please contact your local Cypress sales representative for availability of these parts Document #: 38-05057 Rev. *F Page 9 of 12 [+] Feedback CY62256V Package Diagrams 28-pin (300-mil) SNC (Narrow Body) (51-85092) 51-85092-*B 28-pin Thin Small Outline Package Type 1 (8 x 13.4 mm) (51-85071) 51-85071-*G Document #: 38-05057 Rev. *F Page 10 of 12 [+] Feedback CY62256V Package Diagrams (continued) 28-pin Reverse Thin Small Outline Package Type 1 (8 x 13.4 mm) (51-85074) 51-85074-*F All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05057 Rev. *F Page 11 of 12 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62256V Document History Page Document Title: CY62256V, 256K (32K x 8) Static RAM Document Number: 38-05057 REV. ** *A *B *C *D *E *F ECN NO. Issue Date 107248 111445 115229 116507 239134 344595 493277 09/10/01 11/01/01 05/23/02 09/04/02 See ECN See ECN See ECN Orig. of Change SZV MGN GBI GBI AJU SYT VKN Description of Change Changed from spec number: 38-00519 to 38-05057 Removed obsolete parts. Change to standard format Changed SN package diagram Added footnote 1 Clarified ICC spec for VCC(typ) = 2.5V Added Automotive product information Added Pb-Free packages on page# 10 Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed part # CY62256V25LL from the product offering Updated Ordering Information Table Document #: 38-05057 Rev. *F Page 12 of 12 [+] Feedback |
Price & Availability of CY62256VLL-70ZE
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |